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Home >IC Test & Verification> IC Testing Level
IC Testing Level

Definitions of types & Levels for electronic components testing & verification  

      Level-I Authenticity Inspection & Verification (AIV)

      1. Purpose

Level-I Authenticity Inspection & Verification is a relatively low cost consuming and time-saving test method, which is most applicable for EMS manufacturer and the reseller market. It is a test method used to verify the electronic components conditions through the way of chemical corrosion, physical microscope magnifying observation, simple pin consistency checking etc, to check the intactness of the devices, the surface marking consistency whether the devices are burnished and remarked, the lead/pin integrity and coplanarity etc, which determines whether the devices are consistent with the original manufacturer and requirements of end-user.

      2. Test Items:

A.      Incoming parts backgrounds, external packing (in PVC tubes, trays, paper boxes, anti-static bags, tape & reel, plastic bags with humidity indication cards, vacuum /non vacuum sealed bags, desiccant pouches etc ) inspection, date code, lot number confirmation & relevant records in compliance with OEM’s validity.

B.      External visual inspection, devices surface conditions, OEM specified materials, labeling, marking & logo verification & inspection.

C.      ESD compliance (charge additionally)

D.     Testing & inspection of intactness of pins / leads, balls, moment of force, moment of torque, oxidation degree, solderability ( JESD22-B102D ,if necessary &charge additionally) etc.

100% physical / visual inspection for:

Lead Integrity (JESD22-B105C)

Coplanarity (JESD22-B108A)

Dimensions (JESD22-B100B)

Visual (JESD22-B101 and CECC Inspection Standards)

E.      Verification & inspection of the die layout conditions with multiple electron microscope after decapsulation to identify whether the parts are Counterfeits or not. [Counterfeit products may be able to achieve the original standards(so is called feasible alternatives), or may not be in compliance.]----Chemical Decapsulation is used to confirm original OEM die/chip/wafer (note1)

F.      Micro circuits photos capturing & analysis with microscope to identify whether the surface markings are in accordance with the markings on the die layout. (especially applicable to those parts surface marked with another part number, having similar functions, but actually are burnished & remarked from low-grade parts to simulate high-grade ones. )

G.     Real Time X-Radiography to verify integrity of internal hardware (note 2) as far as the die layout.

H.      Test of some simple electrical parameters.

         Notes:

1. It is a destructive test which has to open the device and inspect the inside chip under high magnification electron microscope, its a perfect way to determine whether the parts are counterfeits or OEMs, the minimum size we can test is as low as 65nm. (Limited to the minimal amount of samples for a lot only).

2. Real time X-radiography to samples are used to verify integrity of internal hardware (chips), the bonding wire, and the excess air bubbles which immerge into interlayer between dies and  packaging materials.

 

Levle-II  Direct Current Characteristics Test (DCCT)

 

Level-II Direct Current Characteristics Test, also known as static parameters measuring test, is a test method performed to measure voltage and current to the records of the DC characteristics to the device parameters through a dedicated IC testing machine (IC tester). A comparative analysis of device performance parameters with original datasheet will be conducted to show the differences. Voltage and current is measured during the DC test and the pass/fail results are based on the measured & compared values.

 
       Test Items:
        

A.  Chemical decapsulation of one random piece of the samples.(default but charge additionally)

B. The testing whether the internal connections are open /short. (The probable affecting factors are various such as environment humidity, corrosion of internal connections / bonding point, some micro metal wire grounded short circuit or bridged some two pins during chips’ packaging process, and the open loop of the pins protecting diodes etc. )

C. The testing whether the input load current limit (IIL /IIH) is in compliance with standard protocols.

D. The testing whether the output threshold voltage (VOH / VOL) is in compliance with standard protocols.

E. The testing whether quiescent current (IDD) is in compliance with OEM requirements & datasheet.

     

      Measure the following DC Characteristic Parameters. 

Direct Current Electronical Parameters

O/S

Open/Short for each pin

IIH

High level input current

           IIL

      Low level input current

             

           VI

   Input Clamp (VI)

 

          RIN

 

Resistive Inputs Pull-ups and Pull-downs

         VOH

        High level output voltage

VOL

Low level output voltage

IOH

High level output current

           IOL

     Output short circuit current

      IOZL/IOZH

      High Impedance Currents

IOS

Output short circuit current

          IDD

      IDD Gross/Dynamic Current

ICC

Operation current

ICCL

Low level supply current drain

ICCH

High level supply current drain

BV

Breakdown voltage

 

Output Fan out

 
 

LEVEL –III KEY FUNCTIONAL TEST (KFT)                                                                       

 

Purpose:

 

For some complex devices, there are no test vector (pattern) provided by OEM. According to the relevant specification, application notes, datasheet & end-users’ application circuit, IC testing lab will firstly have to assess & design a feasible dedicated testing circuit which imposes appropriate and effective incentives (source signals) to the input pins through the external circuits & ports. Then through the regulatory control of peripheral circuits, signal amplification & conversion matching etc, testing lab uses universal measuring instruments / equipments such as the arbitrary signal generator connected to the input pins, while connected to the output pins monitoring the output wave forms with oscilloscope, logic analyzer and spectrum analyzer etc to detect whether the device has defects /errors . The key functional test is a very effective method for those complex devices. Sometimes, it can be executed on the ATE.

 

Test Items:

1. Chemical decapsulation of one random piece of the samples.(default but charge additionally)

2. Verify whether the key functions of the device are consistent with the original OEMs

3. Verify whether the functions can meet the end-user’s requirements. (For the device might meet the original criteria, but not necessarily in line with customer’s needs)

4. Verify whether the device was used or not. (Check whether it has been burned with program or data inside for MCU / Memory/ FPGA)

 

 

LEVEL-IV Full Functions and Characteristics Test (FFCT)

    

           Purpose:

Level IV, FFCT, is an IC testing method performed in accordance with simulation test vectors provided by OEM or written by the testing lab themselves(a relatively more difficult process),  which uses IC testing machine (tester) to test and verify device’s DC parameters, all functional characteristics & performance status, except the testing & verification of AC parameters & characteristics. In other words, FFCT completely covers the test items of Level II &Level III.

Test Items:

A.     The testing items of Level-II & Level-III

B.      Part of testing items can not be achieved by Level-III

C.     Part of electrical limit parameters testing & verification. (E.g. maximum & minimum of VDD, Data writing rate etc.)

Functional Testing

The device actively performs logical functions. Input data is supplied to the DUT and output data is compared with the expected result. Functional testing must attempt to screen out devices which contain marginal defects that could at some future time result in a device failure.

 

Functional testing verifies that the DUT will correctly perform its intended logical functions. To accomplish this, test vectors or truth tables must be created which can detect faults within the DUT. The test vectors, combined with the test timing, make up the heart of the functional test.

 

All aspects of the DUTs performance must be considered when developing the functional test. The exact values of the following items must be carefully examined.

 

       VDD Min/Max DUT power levels

       VIL/VIH input levels

       VOL/VOH output levels

       IOL/IOH output current loading

       VREF IOL/IOH switching point

       Test Frequency cycle time used for test

       Input signal timings clocks / setups / holds / controls

       Input signal formats wave shapes of input signals

       Output timings when will outputs be sampled within cycle

       Vector sequencing start / stop points within a vector file

 

It can be seen from the above list that the majority of the test systems resources must be used during a functional test. All functional tests consist of two distinct components, the test vector file and the instructions contained within the main test program. The test vector file represents the input and output logic states needed to test the DUT. The test program contains the information needed to control the test hardware in a manner that will create all the necessary voltages, wave forms and timings.

 

       Functional Specifications

       Gross Functional Tests

       Test Conditions, Timings, Vectors

       Opens and Shorts - Functional Method

       VIL/VIH Input Levels Testing

       VOL/IOL VOH/IOH Functional Test

       Resistive Output Loading

       Input/Output Levels Relationship

       Functional Z State / High Impedance Testing

 

      

       Open Drain / Open Source Outputs

       Equation Based Timing

       The Test Cycle

       Input Data and Input Signal Formats

       Input Signal Timings

       Output Data and Testing Outputs

       Testing Valid (L/H) Output Levels

       Output Testing using an Edge Strobe or a Window Strobe

       Testing High Impedance (Z-state) Output Levels

       Output Current Loading

       Output Strobe Timing

       Output Loading for AC Tests

       Vector Data

 

 

LEVEL-V Alternating Current Characteristics Test (ACCT)

After the successful completion of level IV testing, of which the parameters of the testing items are in compliance with corresponding criteria & standards, it’s necessary to carry out the Level V ACCT test to further verify the device signals transmission parameters & characteristics, edge characteristics etc (e.g: set-up time, hold-on time, also the use of tools such as Shmoo Plote to analyze the curves characteristics when a variable changes with the change of another variable). ACCT completely covers the testing scope & items of Level IV FFCT, and can solve all the problems FFCT can do & can no do.

AC testing guarantees the device can perform its logical functions with regards to time. There are input timing parameters, output timing parameters and overall operational parameters.

ACCT Testing items including:

A.      The testing items of Level IV

B.      In addition to regular testing items, adopt the analysis way of Sudden second approximation to certain parameters (e.g. linearity mode / binary mode) to identify the signal parameters limits while it changes with other variables, try to analyze the device performance characteristics while it works at different states.

C.      The logical & timing relations between input signals & input signals, input signals & output signals.

D.     The logical & timing relation between system clock & I/O signals.

E.      The signal changing state at the moment of power-up /power-down.

 

AC Parameters Testing

       Standard AC Parameters

       Read & Record and Go–No go Testing

       Compromises

       Rise Time / Fall Time

       Setup Time / Hold Time

       Propagation Delay Measurements

       Minimum Pulse Widths

       Maximum Frequency

       Output Enable and Disable Time

Device Characteristics Analysis

       Characterization Parameters

       Common/Defining Characterization Parameters

       The Linear/Binar Search

       Binary Search Input/Output Timings

       Threshold/Level Search

       Shmoo Plots

 

LEVEL-VI Special Environment Analysis & Test (SEAT)

General description:

Under the premise that all the device parameters of each testing items in Level V ACCT are qualified and in compliance with corresponding criteria & standards, it’s necessary to further

Perform the DCCT, KFT, and ACCT under special environment such as low & high temperature test, high humidity test & vibration test etc to meet special requirements.

 

Testing Items Including:

1.  The testing items of LEVEL-V

2.  Testing of electrical performance &working conditions under special environment.

Additional Test Items and Levels:

LEVEL-EXI ROHS Criteria (Lead-free) Test and Analysis (LFTA)

Therere two branch methods that test whether the device is consistent with ROHS Criteria.

EXI –A Standard ROHS Testing Bar

A special chemical bar can check whether the device is consistent with ROHS

criteria, it is the simplest and fastest way, but not a guarantee

EXI-B Chemical Material Analysis Method

A chemical process is performed to detect,analyze and measure the content & ratio of various components material in the device

 

LEVEL-EXII Solderability Test and Analysis (SDTA)

A chemical method is performed to analyze the ratio of various componetnts material in the device

EXII-A Observe using Microscope

EXII-B Testing of special Measurement & Analysis Instrument for SDTA

EXII-C Observe using other assistant instruments Such as X-Ray , Microsection Analysis, SEM, etc.